1. Field of the Invention
The present invention relates to a semiconductor device which realizes reduction in a device size while maintaining breakdown voltage characteristics, and a method of manufacturing the semiconductor device.
2. Description of the Prior Art
As an example of a conventional semiconductor device, a structure of the following NPN transistor 131 has been known. As shown in FIG. 17, an N type epitaxial layer 133 is formed on a P type semiconductor substrate 132. In the epitaxial layer 133, P type buried diffusion layers 134 and 135 and P type diffusion layers 136 and 137 are formed. The P type buried diffusion layers 134 and 135 expand vertically (in a depth direction) from a surface of the substrate 132. The P type diffusion layers 136 and 137 expand from a surface of the epitaxial layer 133. The epitaxial layer 133 is divided into a plurality of element formation regions by isolation regions 138 and 139 which are formed by connecting the P type buried diffusion layers 134 and 135 respectively with the P type diffusion layers 136 and 137. In one of the element formation regions, for instance, the NPN transistor 131 is formed. The NPN transistor 131 is mainly configured of: an N type buried diffusion layer 140 and an N type diffusion layer 141, which are used as a collector region: a P type diffusion layer 142 used as a base region; and an N type diffusion layer 143 used as an emitter region. This technology is described for instance in Japanese Patent Application Publication No. Hei 9(1997)-283646 (Pages 3, 4 and 6, FIGS. 1 and 5 to 7).
As described, in the conventional semiconductor device, the epitaxial layer 133 is formed on the semiconductor substrate 132. The NPN transistor 131 is formed in the epitaxial layer 133 partitioned by the isolation regions 138 and 139. The epitaxial layer 133 is a region having a lower N type impurity concentration. In this structure, when formation regions of the P type buried diffusion layer 134 and the P type diffusion layer 142 are shifted, a distance L3 between the diffusing layers 134 and 142 is shortened, and a depletion layer stretches over a narrower region. In the NPN transistor 131, the base region and the isolation region is prevented from being short-circuited. This results in a problem that it is difficult to obtain desired breakdown voltage characteristics of the NPN transistor 131. A problem is also caused in which the breakdown voltage characteristics of the NPN transistor 131 are not stable due to a variation in the distance L3.
In the conventional semiconductor device, a thickness of the epitaxial layer 133 is determined in consideration of the breakdown voltage of the NPN transistor 131 or the like. For instance, in a case where a power semiconductor element and a control semiconductor element are monolithically formed on the same semiconductor substrate 132, the thickness of the epitaxial layer 133 is determined depending on breakdown voltage characteristics of the power semiconductor element. The P type buried diffusion layers 134 and 135, which form respectively the isolation regions 138 and 139, expand upward from a surface of the substrate 132 toward the epitaxial layer 133. On the other hand, the P type diffusion layers 136 and 137, which respectively form the isolation regions 138 and 139, expand downward from a surface of the epitaxial layer 133. By use of this structure, lateral expansion widths W4 and W5 respectively of the P type buried diffusion layers 134 and 135 are also increase according to the upward expansion width thereof. In order to realize desired breakdown voltage characteristics of the NPN transistor 131, it is required that the distance L3 between the P type diffusion layer 142 and the P type buried diffusion layer 134 of the isolation region 138 be a certain distance or longer. Thus, there is a problem that the increase in the lateral expansion width W4 and W5 respectively of the P type buried diffusion layers 134 and 135 makes it difficult to reduce a device size of the NPN transistor 131.